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Forum Posts

USART is really working in stmp157 ?

Hi All,i am using stmp157 customize board, with linux yocto build system, and using USART1 configure as a hardware flow control RS 232, and RTO interrupt. and what i found is that CTSIF is not toggling and the proper status are not getting update on ...

Vipul by Associate II
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Resolved! stm32mp135 yocto build process

 i have download prebuild image en.flash-stm32mp1-openstlinux-6-1-yocto-mickledore-mp1-v23-06-21.tar.gzit working fine on my stm32mp135f-dk EVK. i want to add docker in it so need the build process of yocto image.Kindly guide me how to do it.

Can't get mmc2 to see any sd card

I have an stm32mp153aab board with two sd card connections, they are identical except obviously one is connected to sdmmc1 pins and one to sdmmc2 pins.  I have checked schematics and pinmux and everything looks good.  sdmmc1 comes up in both uboot an...

dkal by Associate III
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Resolved! ADC Pin Setup

I am trying to set up 3 ADC.  I set PA4 to ADC1_INP18, PA5 to ADC2_INP19 and PF11 to ADC1_INP2.  Will this be something that works?  I am monitoring 3 lines (none NEED to be fast).I'm not clear on how to set this up.  I am multiplexing several inputs...

SLetter by Associate III
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  • 1 replies
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Resolved! STM32MP15 ECO 5.0.0 u-boot freeze stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 151

Freezes here at rcc setupLooking for rcc@50000000Looking for rcc@50000000- result for rcc@50000000: rcc@50000000 (ret=0)- result for rcc@50000000: rcc@50000000 (ret=0)stm32mp1_clk rcc@50000000: stm32mp1_clk_enable: id clock 151 haslog attached.Any su...

Resolved! Boot from SLC NAND flash vs qSPI

Hi,I consider the boot option for our device. Normally we boot from qSPI EEPROM. STM32MP157 has an option to boot from SLC NAND. Does SLC NAND at STM32P157 have advantages in terms of read/write speed over qSPI? Thank you in advance!

mlytvyn by Associate
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setting MMU on stm32mp157

Please show me a working example of setting up the MMU for STM32MP157D-EV1. and where to place the Translation table correctly (for cortex A7)It is assumed that all data and program will be located in DDR memory, without using the OS 

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