STM32WL5x device errata clarification needed for DMA stream locked when transferring data to/from USART

[CLang.7]

The errata sheet ES0500 - Rev 4 mentions a workaround for 2.8.3 DMA stream locked when transferring data to/from USART where bit 20 of register DMA_SxCR shall be set. This register is not mentioned in the reference manual and not in the respective header files of STM32CubeWL.

Q1: Is the mentioned errata relevant for the STM32WL5x family?

If yes:

Q2: How is the workaround implemented, e.g. where is register DMA_SxCR?

Thanks!

Carsten

[Louis AUDOLY · Accepted solution]

Hello @CLang.7​ welcome to the community,

Thank you for pointing out this issue. This section 2.8.3 do not concern the STM32WL family, we will correct the errata sheet.

Regards

Louis

[GPają.1]

@Louis AUDOLY​ The same problem as described by Clang.7 occur in errata ES0506 - Rev 4.

I have seen section 2.8.3 was removed from ES0500 so it should be corrected in ES0506 also. However problem with DMA still is present on STM32WLE5CCU6. Is there any workaround?