Supported PSRAM and Flash for the STM32N6xx

[RAdam.1]

Hey guys,

I'm looking for some suitable HexaSPI PSRAM and also the OctoSPI Flash for the STM32N645 board I am just building.. I cant find the parts used on the DK so do you have a list of supported memories? I need 256Mb PSRAM and will start with a 1Gb Flash as per the DK.. 

Richard

[RomainR.]

Hello @RAdam.1 

If you refer to the latest External Memory Manager Middleware,
STM32Cube_FW_N6_V1.3.0\Middlewares\ST\STM32_ExtMem_Manager\Release_Notes.html

You will find a list of NOR Flash SFDP from Winbond and Gigadevice manufacturer which are compatible with STM32N6.
Actually, concerning Hexa PSRAM/HyperRAM, only the APMemory APS256XXN-OBR-BG was validated on STM32N6.
After checking, it seems that the APS256XXN is available at Mouser.com.

APS256XXN-OBR-BG AP Memory - Distributors and Price Comparison | Octopart component search

Best regards,

Romain

[johnchargo]

It sounds like I'm in the same position as the original poster.

The recommended PSRAM APS256XXN-OBR-BG is showing as nearing the end of its lifecycle and not recommended for new designs. The manufacturer recommends APS256XXN-OB9-BG as a replacement.

Can anyone comment on the compatibility of APS256XXN-OB9-BG with the N6?

[RomainR.]

@johnchargo 

I reviewed the respective datasheets:

APS256XXN-OBRx – APM Octal PSRAM Datasheet, Rev. 1.00
APS256XXN-OBx9 – APM OPI/HPI Xccela PSRAM Datasheet, Rev. 1.2

The memory devices support the following serial interfaces with the Xcella support on OBx9 part number:
APS256XXN-OBRx: DDR Octal SPI
APS256XXN-OBx9: OPI/HPI and also supports Xccela™ mode for PSRAM

The main differences concern operating frequency and data rate:
APS256XXN-OBRx: Up to 200 MHz (400 MB/s in X8, 800 MB/s in X16)
APS256XXN-OBx9: Up to 250 MHz (500 MB/s in X8, 1000 MB/s in X16)

All other specifications listed below appear to be fully compatible:

Both part numbers are pin-to-pin compatible and share the same package dimensions.
Power-up initialization uses the same method and timing.
Address space, burst type and length, and command/address latching are identical.
The command truth table is the same.
Read operations use the same address/data transfer sequence and timing.
Write operations also appear to be aligned.

In my opinion, the APS256XXN-OBx9 should be compatible with STM32N6 XSPI without any modifications but limited to 200MHz with DQS.

Best regards.
Romain,

[Alex - APMemory]

Hi, 

Just to add few comment:  APS256XXN-OB9-BG - 256Mb is recommended latest device to use (APS512XXN-OB9-BG - 512Mb). This is latest version in production, fully compatible with STM32N6 (and other STM32 MCU supporting OPI). (APS256XXN-OBR-BG is the lower speed grade, not recommended for new design)

Thanks

Alex

[RomainR.]

Hi @Alex - APMemory 

Thank you to have confirmed the point.

Best regards,

Romain,

[uiths]

Hi Romain,

do you know of any OctoSPI PSRAM with 128MB (1024Mb) that is compatible with the STMN6?

Thanks in advance

[Alex - APMemory]

Hi, 

You can use 2 pces of 512Mb (ASP512XXN-OB9-BG) and 2CE to make 1Gb on same memory controller

Method 1 : Optimize performance, need 2 controller and more pin (two PSRAMs can be treated as independently controlled devices)
Method 2 : Double density without controller / pin count impact. Note: due to path loading, you might need tu use IBIS simulation to confirm the data window is good enough.

Regards

Alex

[uiths]

Thanks for the fast response!

Which method would you suggest? How would the memory be accessed when using method 1? Will the hardware handle everything and I can assume it being continuous RAM when programming the firmware? If I understood the Datasheet correctly the FMC has two ports, so with Method 1 I wont be able to add another OctoSPI flash for the firmware to the MCU, right?

Best Regards

[Alex - APMemory]

if you  have 3 memory devices (two PSRAM and one NOR), with only 2 xSPI/OPI memory controller, you will be in method 2 anyway. One controller with 2 device, one controller with one device.

You can decide to have

a) the two PSRAM on one controller and NOR alone

b) one PSRAM and NOR on one conttroler, and PSRAM alone

This may be driven by your SW architecture, and whether the PSRAM usecase can be splitted or not, and if yes, which usecase need more performance. No general recommendation, just as one example, you may decide to do frame buffering on the xSPI, and share NOR / PSRAM for code / data. 

Alex