I wish to see an example of using DAC2 (not DAC1 Channel 2) using bdma2 on an stmh7 mcu. I am thinking that the memory used lies in the SRD memory location : RAM_SRD (xrw) : ORIGIN = 0x38000000, LENGTH = 32K on a stm32f7a3zitq.

Claydonkey · ‎2022-06-17

I would need assistance in editing the linker script and the startup (.s) file to access the memory area from a c routine...

Claydonkey · ‎2022-06-26

After a week of hair pulling, I finally solved it: For those trying to get the DAC2 on STMH7A chips. This is the secret:

In the linker script the SRD ram is listed. It is 32k in Length which should suit most DAC applications.

MEMORY
{
  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 2048K
  DTCMRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
  DTCMRAM2 (xrw) : ORIGIN = 0x20010000, LENGTH = 64K
  RAM (xrw)      : ORIGIN = 0x24000000, LENGTH = 1024K
  RAM_CD (xrw)   : ORIGIN = 0x30000000, LENGTH = 128K
  RAM_SRD (xrw)  : ORIGIN = 0x38000000, LENGTH = 32K
}

So you need a definition of this memory area in the script in order to define it in gcc:

.DATA_RAM_SRD (NOLOAD) :
  {
  } >RAM_SRD

In your C file:

uint16_t m_array[ARR_LEN] __attribute__((section(".DATA_RAM_SRD")));

Hey presto. DAC2 will behave like DAC1 (with 1 channel only). From what I can see it has the same specs as DAC2 except no FIFO and it can only synchronise with peripherals in the D3 domain (RCC Clock etc)