STM32G474RB CubeMX ADC Clock Mux is swapped

[janik]

Hello,

the STM32G474RBTx CubeMX Clock Configuration ADC1_2 and ADC3_4_5 are swapped - the ADC1_2 Mux is actually referring to the ADC3_4_5 Mux, at least when it comes to the subsequent divider options in the respective ADC configurations.

Setting ADC12 Mux to PLLP with e.g. 48.57 MHz allows me to put ADC3_4_5 into ASYNC_DIV_1, whereas the ADC3_4_5 Clock Mux is set to SYSCLK with 170MHz. ADC12 cannot use ASYNC_DIV_1 or 2, even though they should be able to.

It also happens the other way around.

I am using CubeMX 6.17.0 with the G4 package version 1.6.3

[Mahmoud Ben Romdhane]

Hello  @janik 

Let me thank you for posting.

For more investigation, I recommend that you provide the Ioc.File.

Thanks.

Mahmoud

[janik]

Hi,

I have attached a basic ioc demonstrating the bug. observe that you cant set ADC12 to ASYNC_DIV2 or DIV1, even though its clock is approx. 48.57 MHZ.

[Mahmoud Ben Romdhane]

Hello @janik 

Let me thank you for bringing this issue to our attention.

This issue has been escalated internally to the dedicated team and tracked by Internal ticket number: CDM0062851 (This is an internal tracking number and is not accessible or usable by customers.)

A fix will be implemented in the upcoming releases of STM32CubeMX.

Thanks.

Mahmoud