STM32L4 DMA latency for ADC to SRAM transfer

[Markus Vogel]

Posted on April 07, 2017 at 10:27

Hello everybody,

I have the following situation:

• Processor STM32L476
• 48MHz HSE
• I want to sample an external signal at 4MSPS. Therefore I use 60MHz PLLSAI1 as ADC1's clock
• This gives 4MSPS (with 2.5cycles sampling and 12.5 cycles conversion - 12bit resolution)
• ADC1 runs in asynchronous mode and shall sample 4096 points
• Data are transferred by DMA1, Channel1 to internal SRAM

My question now is:

• I want to minimize the HCLK to save power
• So what is the minimal HCLK such that the DMA transfer would still work, i.e. how long does the DMA transfer ADC1 to SRAM take?

What I found out so far:

• Transfer seems to work when HCLK/(ADC sampling clock) >6 (ADC sampling clock is 4MHz for my 4MSPS), so e.g. I found it works for 24MHz HCLK and 3.73MSPS (ratio is 6.42), works sometimes for 24MHz HCLK and 4MSPS (ratio is 6), never works for 24MHz HCLK and 4.27MSPS (ratio is 5.63)
• For other processors I found application nodes AN4031 which give delays of 9 AHB cycles, but I guess I found better results for STM32L476, so I don't think these values fit there

#adc-dma #stm32l4 #stm32 #dma-performance

[Markus Vogel]

Posted on April 07, 2017 at 10:29

Pardon me for the bad manners - I pressed Enter to soon. Here is the proper ending of my post:

Hope you can help me with my problem.

Kind regards

Markus

[waclawek.jan]

Posted on April 07, 2017 at 11:04

For the 'L4 DMA, probably AN2548 is appropriate, even if it talks about F1/L1 - I believe the DMA in 'L4 is the same/similar than that in 'F1/'L1/'F0/'L0 (and quite different from that found in 'F2/'F4/'F7). However, the total transfer time calculation is not trivial and in your case might be quite different from what's given there, as:

- there may be simpler/shorter arbitration within the DMA if only one channel is used

- there may be simpler/shorter arbitration on the AHB/APB bridge if the AHB/APB clock is 1:1

- there may be simpler/shorter arbitration on the bus matrix if processor won't access the shared resources (SRAM, APB) ever

It may quite well be that you've already found the sweet spot.

JW