Wrong PLL prediv calculation in LL driver when using the HSE?

[Martin Rm]

Posted on April 05, 2018 at 14:10

Hi,

I think there is a possible BUG in LL libraries when using the HSE.

My controller is a stm32f103t8 with an external Oszillator.

I use LL version V1.1.1.

The following function in stm32f1xx_ll_rcc.h should return the prediv factor for the PLL.

__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)

{

&sharpif defined(RCC_CFGR2_PREDIV1)

  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));

&sharpelse

  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));

&sharpendif /*RCC_CFGR2_PREDIV1*/

}

The problem is now that this function returns the bit value in that register, here 2^17 if set - not the factor itself

The function RCC_PLL_GetFreqDomain_SYS() in stm32f1xx_ll_rcc.c calculates the pll input frequency in that way:

...

case LL_RCC_PLLSOURCE_HSE:       /* HSE used as PLL clock source */

   pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);

   break;

...

The result is that the HSE_VALUE is divided by the bit position 2^17, the result is a wrong pll frequency.

The problem is that this functions is called indirect in LL_USART_Init, i2c and more. So the USART doesn't work

with the HSE in F1 LL drivers.I think in the function LL_RCC_PLL_GetPrediv above is the shift operator missing in that way:

return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos)

Or do I have missed something?

Thank You

#ll-bug #hse #stm32f1 #bug?

[Imen.D]

Posted on May 11, 2018 at 17:53

Hello

Rohrmoser.Martin

,

This issue is raised internally to the developer team, then we will keep you informed about the taken actions.

Best Regards,

Imen.

[Imen.D]

Posted on July 13, 2018 at 15:26

Hi 

Rohrmoser.Martin.001

,

We have reproduced this issue from our side for LL_RCC. The return value of LL_RCC_PLL_GetPrediv() was 2^17 and it should return the PREDIV factor for the PLL.

This issue will be fixed in the coming version of CubeF1.

Thanks and Best Regards,

Imen