STM32N657X0H3 QSPI and SDRAM Integration

[Ajnas-C]

Dear Team,

We are currently working on a project based on the STM32N657X0H3Q MCU. As part of our design, we are planning to use a QSPI Flash and SDRAM instead of the OctoSPI Flash and HexaSPI PSRAM used in the reference designs.

Could you please share any reference schematics, application notes, or design examples that demonstrate the integration of QSPI Flash and SDRAM with the STM32N657X0H3Q?

Additionally, our design is highly space-constrained. If anyone has a reference for a minimal power supply/regulator design for the STM32N657X0H3Q, we would greatly appreciate it if you could share that as well.

We look forward to your response and guidance.

Thank you for your support.

Best Regards,
Ajnas C

[mƎALLEm · Accepted solution]

Hello @Ajnas-C and welcome to the ST community,

AN4760 "Introduction to Quad-SPI interface for STM32 MCUs and MPUs"

To my knowledge there is no reference design STM32N6 + QSPI but you can inspire from other platforms like STM32H7 (STM32H743-EVAL schematic )

Same thing for SDRAM:

How to set up the FMC peripheral to interface with the SDRAM IS42S16800F-6BLI from ISSI

Good luck. 

[Ajnas-C]

Hello @mƎALLEm 

Thank you for your response and for sharing the reference documents.

I am relatively new to the STM32 platform and would appreciate your guidance.

Could you please confirm whether the STM32N657X0H3Q supports the following configuration:

QSPI NOR Flash (instead of Octal Flash)
External SDRAM (instead of HexaSPI PSRAM)
Our goal is to use a more cost-optimized memory solution for our design.

Additionally, could you please clarify the following:

1. Are there any limitations or restrictions when using QSPI Flash as the primary external boot memory on STM32N657X0H3Q?
2. Is there any recommended SDRAM size, bus width (16-bit or 32-bit), or memory device family that has been validated with STM32N6?
3. Is there any hardware design guideline available for a minimal power supply implementation using the internal SMPS of STM32N657X0H3Q, especially for space-constrained designs?
4. Are there any example projects, CubeMX configurations, or application notes demonstrating QSPI Flash + SDRAM operation on STM32N6 devices?
Your guidance will help us finalize the memory architecture for our design.

[mƎALLEm]

Hello,

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@Ajnas-C wrote:

3. Is there any hardware design guideline available for a minimal power supply implementation using the internal SMPS of STM32N657X0H3Q, especially for space-constrained designs?

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That's a new question. You need to open a new and dedicated thread for it.

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@Ajnas-C wrote:

4. Are there any example projects, CubeMX configurations, or application notes demonstrating QSPI Flash + SDRAM operation on STM32N6 devices?
Your guidance will help us finalize the memory architecture for our design.

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I've already said that there is no reference design for it. And you need also to open a dedicated thread for it.

In the community we should handle one question per thread.

Thank you for your understanding.