Hi,
I'm buiding a custom board which involve STM32H753XIH6 and IS42S32800J-6TLI, I noticed that STM32H7B3-EVAL schematic has the following:
The SDRAM (IS42S32800J-6BL) does not use A12 and A13 — only A0–A11 are connected.
The Bank Address pins (BA0, BA1) of the SDRAM are instead connected to FMC_A14 and FMC_A15.
This raises my question:
Why does the STM32 FMC map BA0/BA1 to FMC_A14/A15 specifically, instead of FMC_A12/A13?
Can you confirm if the schematic is correct for this SDRAM interface given the below configuration.
Thanks,
Moahmmed
1 ACCEPTED SOLUTION
Accepted Solutions
> Why does the STM32 FMC map BA0/BA1 to FMC_A14/A15 specifically, instead of FMC_A12/A13?
FMC_A12 (PG2) doesn't have FMC_BA0 as an option. FMC_A14 (PG4) does. That's the only pin on this chip that has that function, so that's why it's used.
Posted schematic looks good to me.
> Why does the STM32 FMC map BA0/BA1 to FMC_A14/A15 specifically, instead of FMC_A12/A13?
FMC_A12 (PG2) doesn't have FMC_BA0 as an option. FMC_A14 (PG4) does. That's the only pin on this chip that has that function, so that's why it's used.
Posted schematic looks good to me.
