Hello,
I'm looking into a potential 8-bit wide bus to transfer data between a STM32F765VIT (LQFP100) and a MAX10 FPGA which are close to each other (less that 30mm), to potentially back up a USART link between the 2. The goal is to be able to reach transfer rates of at least 10 MTps.
I have already figured out (using AN4666) that I want to use DMA+GPIO to avoid overcomplicating thinkgs with the FMC.
Right now, here is my hardware design (with bits of software considerations) :
- 8 bit data bus using PE9 through PE15, configured as Open-drain, pulled-up to VCCIO (3,3V) with 330 ohms external. Corresponding pins on the MAX10 are also set to open-drain bidir
- 1 CS signal, push-pull on the STM32F765, used to indicate to the (slave) MAX10 if it can take the bus. This is on pin PB10.
- 1 CLK signal, routed on both pins PB0 and PB1 (these are close the PE7-PE15). On PB0, TIM3_CH3 is set to PWM generation, to generate the data clock in case the STM32 is transmitting. On PB1, TIM3_CH4 is set to input capture (direct) to catch rising edges in case the MAX10 FPGA is transmitting (both clock and data). This would also be open-drain externally pulled-up to 3,3V through 330 ohms
- 2 FIFO signals, indicating FIFO empty and FIFO half-full. These are also bidirectionnal, so set up as open-drains and externally pulled-up
I will be using TIM3_CH4's input capture to trigger the DMA transfer from GPIOs PE8-15 to memory, and TIM3_CH3's PWM output to trigger the DMA transfer from memory to GPIOS.
As of now, the risks I see are :
- Using the same TIM3 for input capture and pwm generation means that I have only 1 reload register. However I don't think it is important since I want to request the DMA on EVERY input capture rising or falling edge. Am I correct ?
- Can every DMA channel interface every GPIO bank ? I have not seen this info, and I am wondering if TIM3 can even trigger to right DMA and DMA channel to fetch data to and from GPIOs PE8 through PE15.
- How can I transmit FIFO status pulses without CPU involvment ?
What do I need to watch out for ?
Considering the fabrication delays, completely implementing the software first would set me back tremendously, this is why I am asking for advice here. I use CubeMX to see what options I am allowed on pins/peripherals.
Thank you for your help.
