I am using the STuW81300 as LO generator to generate 12GHz LO. Although I am able to get the frequency out correctly and the PLL is also locking the output power of the signal us at -39dBm (probing) where ideally it should be giving close to -4dBm.
The is some difference in the LOOP FILTER section of my schematic compared to the EVB schematic. Other than this I cannot understand why it is not giving the said output power. I seriously doubt that this could be the cause for this as the PLL is locking and I am able to generate the required frequency.
I am also attaching the Schematic for reference as well as the register initialisation mapping is also given below.
0x9,0x48000000
0x8,0x40000003,
0x7,0x39000000
0x6,0x30001000
0x5,0x28000000
0x4,0x20039115
0x3,0x18008002
0x2,0x1000000A
0x1,0x09400001
0x0,0x03E0003C
