IPCC interrupt issue in stm32mp157A ?

[Srikanth1]

Hello,

We are using STM32MP157A.

We are working on IPCC from A7-0,A7-1 to M4.

We are getting IPCC interrupt A7-1 to M4,But when we are not getting interrupt from A7-0 to M4.

In cubeMx it is showing NVIC to IPCC RX1 and TX1, but not showing to RX0,TX0.

we are using CubeMX 6.3.0 and firmware version is STM32Cube_FW_MP1_V1.4.0.

But in reference manual showing IPCC_RX0,IPCC_TX0 these interrupts are available.

 

in our application we need interrupts both A7_0 ,A7_1 processors to M4 controller.

please help us in this regards.

regards

srikanth

[PatrickF · Accepted solution]

Hi,

there should be no issue, IPCC if full duplex and provide one interrupt channel from A7 to M4 and one interrupt channel to M4 to A7.

• IPCC RX1 and TX1 interrupts has been chosen in our SW deliveries to be the interrupts on Cortex-M4 side
• IPCC RX0 and TX0 interrupts has been chosen in our SW deliveries to be the interrupts on Cortex-A7 side

See https://wiki.st.com/stm32mpu/wiki/IPCC_internal_peripheral#Overview

For Linux kernel, the interrupt management could be done by either processor #0 or #1, but only one processor at a time (I'm not Linux SW expert). This behavior is likely managed by relevant GIC interrupt routing settings during Linux run time.

I guess Linux kernel will then distribute maibox events to relevant SW tasks.

Although from GIC HW point of view you can enable IPCC RX0 and TX0 interrupts to both A7#0 and A7#1, that's generally not a good idea as there could be interrupt management SW timing courses on both CPUs which might need semaphore management which will impact interrupt latency.

Regards.