STM32H7xx - PLL input frequency range settings

[JPoha.1]

Hello,

this is a description of PLL settings from a reference manal

00: The PLL1 input (ref1_ck) clock range frequency is between 1 and 2 MHz (default after reset)

01: The PLL1 input (ref1_ck) clock range frequency is between 2 and 4 MHz

10: The PLL1 input (ref1_ck) clock range frequency is between 4 and 8 MHz

11: The PLL1 input (ref1_ck) clock range frequency is between 8 and 16 MHz

What should I set if my PLL input is exactly at the boundary? Eg 8MHz.

BR

Jan

[Uwe Bonnes]

Choose depending on the real frequency 8.000001 or 7.999999 <joke> . Choose any, it should not matter.

[JPoha.1]

Thanks for reply. I know that both is working :)

Do you know, what these settings actually do and what happens if the difference would be bigger?

[waclawek.jan]

PLL is a semi-analog circuit, especially the phase-detector and subsequent filter. There's tradeoff between lock time, jitter and stability in its design. I'd say, this parameter controls this part of the PLL, setting it to a tested optimal state for given input frequency.

> what happens if the difference would be bigger?

Probably the parameters given in DS won't be met under all possible circumstances (power supply voltage range, temperature range).

JW