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STM32H743VGT6 flash memory

JBond.1
Senior II

Hi, I have bought STM32H743VGT6 and want to make bootloader and application. The issue is that its memory layout is confusing. In documentation and generated application I see/assume flash memory is:

0x8000000 size 0x80000 (512kb bank1?) // bootloader
0x8100000 size 0x80000 (512kb bank2?) // application

But when I try to write to 0x8100000 I get "Error occured during memory writing!". Instead I can write to

0x8000000 size 0x100000 (1024kb)

Does this mean I have only Bank1, but no Bank2? Can I still do bootloader which is on Bank1 and writes to flash on same Bank in different sector? How can it be that I have only one Bank?..

1 ACCEPTED SOLUTION

Accepted Solutions

>  512kb then gap then 512kb

Yes.

> is it possible to run erase/write code from bootloader in bank1 sector1 to erase/write bank1 sector2?

Yes. While erasing, the flash will stall other accesses to the same bank (for example retrieving interrupt vector of the systick). Real-time activity may break.

If you doubt about your Keil version, please use recent CubeProgrammer.

 

 

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7 REPLIES 7
Pavel A.
Super User

STM32H743VGT6 should have two banks * 512K as in your post. However, other STM32H743 models have two banks * 1024 K  (0x100000). Also, even some 512K per bank models may actually have more than 512K writable, but the extra memory is not warranted.

Please include the entire error log from CubeProgrammer or whatever you use to write.

 

 

>Please see and confirm.

Per the RM0433, table 16 address 0x08100000 is sector 0 of bank #2.

Or, with bank swap activated, sector 0 of bank #1.

(I don't have exactly this chip, can't test- sorry)

AScha.3
Super User

These H743 chips with variants, are basically same die for different flash size:

and all are 450 die :

AScha3_0-1779549566550.png

 

Reason is: for the purpose of rationalized production only one die is produced , with 2MB .

Testing the flash is "expensive" on the chip tester, so short test -> smaller flash tested -> cheaper version.

So you have a chip with 2x 512K flash, tested and 100% working - as you ordered.

See: https://community.st.com/t5/stm32cubeprogrammer-mcus/cube-programmer-shows-256-pages-of-2k-in-a-256k-mcu/m-p/898515#M10136

 

Check with CubeProgrammer, what its telling:

here i connect a H743ZG  , 1MB flash (but die has 2MB :)

AScha3_1-1779549861993.png

 

 

If you feel a post has answered your question, please click "Accept as Solution".

I am using Keil, Maybe its mostly old version of Keil issue

File       : D:\Programs\Keil_v5\Packs\Keil\STM32H7xx_DFP\4.1.3\Keil.STM32H7xx_DFP.pdsc 
Sequence   : DebugDeviceUnlock -> CheckID 
Context    : Item #0: <block>::Line 10 
Expression : "ams\Keil_v5\Packs\Keil\STM32H7xx_DFP\4.1.3\Keil.STM32H7xx_DFP.pdsc" 
E310       : Debug access failed - cannot read address 0xE00E0FE4 (accsize '4', AP '0x00000002')
 
Internal parameter error
No Algorithm found for: 08100000H - 0810D5CBH
Erase skipped!
Error: Flash Download failed  -  "Cortex-M7"
Flash Load finished at 19:15:35

However I was able to write to flash from bootloader itself. My current setup is this: (I assume its correct one? with fully testeed flash of 512kb then gap then 512kb?)

0x8000000 size 0x80000 (512kb bank1) // bootloader
0x8100000 size 0x80000 (512kb bank2) // application

Additional question would be, is it possible to run erase/write code from bootloader in bank1 sector1 to erase/write bank1 sector2? Or you always must erase/write to another bank?

It's not just that Testing the FLASH is expensive. Sometimes part of the FLASH fails. It just takes the tiniest speck of dust in a clean room that has fewer than 100 dust particles per cubic metre of air. It's normal to be able to reconfigure the addressing of FLASH, and generally a few spare blocks are included to optimise the number-of-good-chips versus the area used by each chip for maximum profit.

But sometimes more blocks fail than can be made up by the spare ones. And under those circumstances, if it's possible to reconfigure it as a smaller-FLASH part and sell it as that, they will do so.

Another thing to point out is that ST guarantee their memory cells will survive a certain number of write-erase cycles. Their tests are probably sufficiently sophisticated to sense that although a particular cell seems to work now, the analog voltages suggest it might fail early. So they will treat it as bad. You might find that it programs OK the first few times you use it.

(I remember many years ago a particular home computer had its 48k of RAM made from one set of standard 16Kx1 DRAM chips and a second set of 32Kx1 DRAM chips, at a time when you could only buy 16k or 64k chips. The canny manufacturer would buy up failed 64k chips and only use one half)

>  512kb then gap then 512kb

Yes.

> is it possible to run erase/write code from bootloader in bank1 sector1 to erase/write bank1 sector2?

Yes. While erasing, the flash will stall other accesses to the same bank (for example retrieving interrupt vector of the systick). Real-time activity may break.

If you doubt about your Keil version, please use recent CubeProgrammer.