STM32F4xx peripheral to memory max rate

denny23 · ‎2012-11-01

Posted on November 01, 2012 at 18:35

I have a peripheral bursting 8-bit parallel data at 56MHz gated by a data valid signal. Can the STM32F4xx support peripheral to memory dma at this rate? What is the max rate the STM32F4 can handle dma requests?

#stm32-dma

Tesla DeLorean · ‎2012-11-01

Posted on November 01, 2012 at 19:00

Not sure there are clear metrics for this. I'm sure one could benchmark using a timer and get an upper level for saturation.

APB1 is limited to 42 MHz, APB2 is limited to 84 MHz, but these are 32-bit wide buses. I would imagine an uncontended DMA transaction would take several cycles.

8-bit width kills you on bandwidth. Is this data coming from an external source?

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denny23 · ‎2012-11-01

Posted on November 01, 2012 at 21:10

The data is from an on-board peripheral chip that burst out data at the chip's clock rate as it becomes available and does not have FIFOs to smooth out the bursts.