STM32F4 I2C CR2 Peripheral clock frequency

[LGrüb.1]

Dear Forum,

I'm using a STM32F401 and implemented the I2C as Target transmitter (Slave) answering a I2C question. 

I'm programming the I2C CR2 (FREQ Bits) Register as follows with correct speed (42 MHz)

I2C1->CR2 = ((DRV_RCC_GetPCLK1Freq() / 1000000u) & I2C_CR2_FREQ_Msk);

 I've noticed some spikes when the STM32 I2C controller generates the answer, see below (yellow markings)

Blue: Clock generated by the controller (the clock speed is about 200kHz)

Red: Adrdess Byte generated by the controller, Data Bytes generate by STM32 I2C transmitter (answer) with spikes

When the FREQ Bits of I2C_CR2 Register are zero, this spikes doesn't occur, see below

The Reference Manual RM0368 Rev 6 for the I2C CR2 writes:

It is noticed that this FREQ bits must be configured to generate I2C compliant Signals. Anyhow from EMC perspective this spikes are bad because the radiate a wide spectrum. I've found nowhere information of correct I2C specifiation/behaviour of the Data Signal the be compliant, anyhow the data is transfered correctly to the controller.

Q: must the FREQ bit of CR2 be set in slave mode?

Q: what is I2C compliant behaviour

Q: How about CCR Register, is it neccessary to set in slave mode (how to set the I2C_CCR_FS Flag)?

Q: Is this Standard or Fast Mode (because of 200 kHz clock)?

Q: TRISE Register doen't show any influence if this case, is it of any concern?

Thank you for your thoughts and time.

regards,

Lorenz

[jiangfan]

The Reference Manual RM0368 Rev 6 for the I2C CR2 writes: FREQ = 0 is not allowed. so, user should follow this requirement. If you want to reduce the EMC output from I2C, you may configure I2C pins GPIO speed to LOW, then EMC radiation is low.

[LGrüb.1 · Accepted solution]

Hello jiangfan,

thank you for reply, GPIO speed to LOW helped for reducing EMC, anyhow I2C is working fine

regards

Lorenz