Posted on October 16, 2014 at 09:03
#1: why is there a slope when it should be an sharp edge?#2 and #3: why do they exist? Are they caused by noise? The pulse width of #3 is about 18us.#4: It is suppose to be logic LOW in this period, why are there so many spikes whose width is about 0.1us. The even funny thing is, when I set duty cycle to 101%, those spikes disappeared! It is shown in next picture where dutycle is 101%.#5: the first pulse width is the same as #3 followed by spikes.The result when duty cycle is set to 101%!
All three channels showed the same problems. Would anyone please advise why are those problems happening?
I am trying to implement 3-phase BLDC drive signal based on Hall effect inputs. I chose TIM1 CH1(PA8), CH2(PA9) and CH3(PA10) as PWM outputs with complement output enabled (PB13, PB14 and PB15). TIM_OCPolarity and TIM_OCNPolarity are set to LOW, Output state during idle set to *_Set, PWM freq is 40KHz
When I set PWM duty cycle to be 100%, something strange happened, as shown in the picture below. Yellow is CHx and Green is CHxN.#1: why is there a slope when it should be an sharp edge?#2 and #3: why do they exist? Are they caused by noise? The pulse width of #3 is about 18us.#4: It is suppose to be logic LOW in this period, why are there so many spikes whose width is about 0.1us. The even funny thing is, when I set duty cycle to 101%, those spikes disappeared! It is shown in next picture where dutycle is 101%.#5: the first pulse width is the same as #3 followed by spikes.The result when duty cycle is set to 101%!All three channels showed the same problems. Would anyone please advise why are those problems happening?
