Posted on April 28, 2015 at 20:37We are using the same SDRAM on our board as stm32f429i-disco and my question is about
the example code - STM32F429I-Discovery/Examples/FMC/FMC_SDRAM/Src/main.c
where the initialization is only for BANK2, please confirm.
Has anybody used and can provide the initialization for all
4 banks of IS42S16400J SDRAM ?
stm32f4xx_ll_fmc.h only provides for BANK1 and BANK2:
/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
* @{
*/
&sharpdefine FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
&sharpdefine FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
&sharpdefine FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
/**
* @}
*/
main.c calls the initialization :
static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
{
__IO uint32_t tmpmrd =0;
/* Step 3: Configure a clock configuration enable command */
Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = 0;
-
The 64-Mbit SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3 V memory systems containing 67,108,864 bits. it is internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64-Mbit SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK.
The STM32F429ZIT6 MCU reads and writes data at 80 MHz.
#stm32f429i-disco-fmc-is42s16400j
