GPIOs in low power when a defined output is required ?

[Andrew Neil]

I know that, for lowest power, it's recommended to switch GPIOs to analogue in.

But I require outputs to keep a defined level during low-power (STOP).

As far as an STM32F030 is concerned, is there any power consumption advantage to choose between using push-pull and open-drain (possibly with pull-up/down) ?

[waclawek.jan]

I believe that as far as power consumption (except what's drawn/pushed by the external circuitry from/to the GPIO pins in question) there's no difference between pushpull (with no pullup/pulldown), open drain (where pullup would be switched on only when output is NOT set to 0) and Input with pullup or pulldown as appropriate.

This, assuming that the nominally 40k pullup/pulldown is sufficient to supply whatever external current is to be drawn.

JW

[Andrew Neil]

Sidekick says:

Push-Pull vs. Open-Drain in STOP Mode

While the documentation does not provide a direct comparison between push-pull and open-drain configurations in STOP mode, it emphasizes that push-pull is generally preferred for maintaining a defined output level with minimal consumption. Open-drain may be used in specific cases, but it typically requires an external pull-up resistor, which could increase power consumption depending on the resistor value and the state of the pin.

It references Tips for using STM32 low-power modes, which does say:

Perhaps in one situation where a device connected to a GPIO is still on when the GPIO is set to analog mode, this could leave the pin in floating state and cause toggling on the other device. In this situation, it may be better to leave the GPIO in a known push-pull state, which has minimal consumption to begin with. Consider all external connections when deciding which configuration is best

But gives no discussion of justification of push-pull vs open-drain or using internal pullups.

Also AN4899 GPIO software guidelines for power optimization, but that also doesn't seem to consider the choice between push-pull vs open-drain or using internal pullups.

[waclawek.jan]

AI, of course, cannot bring anything useful to this discussion, by principle, as it's just a noisy rehash of whatever real information is out there, and you've already read all that.

While there is no detailed public documentation on the IO structure to infer this directly, I see no reason why would open drain be implemented in any other way than just have the upper power transistor OFF all the time. If that's the case, having GPIO Out in PP at 0 is exactly the same as GPIO Out in OC at 0. This, of course, provided the pullup is off for this case. And, assuming the leakage of the closed lower power transistor is far less than the 40kOhm nominal resistance of the pullup, which it certainly is, the consumption in 1 will be the same for PP and OC, too.

Now the difference between using GPIO Out and In-with-Pull-up-or-down boils down to difference in leakage of the Pull's serial transistor and the Out's power transistor. I guess, the latter is dominant, as the Out transistor will be significantly wider to provide several orders of magnitude more current than the Pull's serial transistor needs to (although it does not mean it is not also longer, decreasing leakage, but probably not or not significantly). Whichever it is, note, that worst case it's just twice the current of the case when *both* transistors in *both* Out and Pull are OFF - and they are, for all pins which don't output or pull some output level, even in Analog mode. And also note, that the 'F030 (depending on which one - they are of 3 different dies) - has around 30-60 IO pins altogether, and the total leakage of the whole chip (i.e. the lowest-power-mode except VBAT) is around 1uA at room temperature, so that's say 30nA per pin's IO structure; and as I've said above, using whichever mode to achieve a stable output level, means twice as much, i.e. cca 60nA per pin. Plus or minus.

But... there's one more source of power consumption, and that a potentially dominant one. The GPIO In structure. That's active also in Out mode (and AF too). Now it's said to leak less than 1uA per pin, which in itself is much; I've lazily measured a 'F3 pin in In and it sunk cca 0.3uA from VDD=3V. I wouldn't call that exactly leakage, as IMO it's a deliberate superweak pull to get a floating pin to a defined level, or part of the hysteresis mechanism, or both. That may be also one of the reasons why ST recommends to switch pins to Analog for low consumption modes. And as in 'F0 there's no way to influence output level in Analog mode (except perhaps for DAC, but that is probably off (is it? maybe not. but that's still just 2 pins max)), you're stuck with it. So  I'm afraid, that that digital input structure's leakage going to be the dominant source of leakage, at least when output is set to 1, regardless of how is it set to 1.

I may have mentioned that there are newer families - e.g. 'G0/'C0/'U0 - which may have better means of achieving GPIO output levels in the lowest-power modes.

JW

[Andrew Neil]

---

@waclawek.jan wrote:

AI, of course, cannot bring anything useful to this discussion, by principle, as it's just a noisy rehash of whatever real information is out there, and you've already read all that.

---

At least Sidekick did cite its sources!