ADC reading without phase delay

[STuser2]

I have a requirement from customer to read the mains input voltage (down converted to 3.3V) which is 50Hz using ADC and identify the phase delay between the input and after the ADC reading(Ideally it shall be 0 requirement). How to demonstrate? I am using STM32G474RET6. Please guide.  

Edit: I am trying to trigger ADC sample at every 20KHz PWM signal.

[AScha.3 · Accepted solution]

Zero delay is impossible, the ADC needs 0,25us to convert, so at 50 Hz about 0,0045°.

To "prove" ds is correct, maybe : read ADC and write data direct to DAC , to view output with scope.

But this will add about 1us for data handling , DAC conversion time and settling.

So should show about 0,02° at 50 Hz .

btw

Show this on a dual trace scope, 50Hz -> 20ms, at 2ms/div setting you can see no delay , because 2us delay would show as 0,01mm on screen...not visible. So you can show: no delay (visible). :)

[STuser2]

Only for re confirmation i get the below values

0.0045 and 0.02 Degrees  i get a factor 0.1 less, can you please confirm if i am making any mistake?

[AScha.3]

I just used online calculator...

1us -> 0,02° ....and wrote one zero too few... :)  

Your right.

(corrected now.)

[STuser2]

I was understanding the sampling time of 0.25uS and 1uS, has gone through the below video from ST

Hands-On with STM32 Timers: Trigger Periodic ADC Conversions

He setup the timer for 10KHz sampling and toggles the pin in ADC ISR which toggles at every 10KHz, but is this inherently wrong as he is not considering the sampling time and conversion time?

[AScha.3]

No, nothing wrong . ADC conversion -inculding sample time- is fix, as clock and sample giving the time in cycles;

see ds: G474

So the toggle just shows, the ADC conversion taking place now, at this rate - not how many us it needs.

The conversion is much faster than the cycle time.

At high speed setting, conversion needs about 0.25 us , at 10kHz = 100us interval, still about  99% "free" time for the cpu to do something with the data ; and if using a timer to start ADC and DMA to put data to an array or circular buffer, cpu 100% free time, to do ...anything.

If going for high speed conversion, this ADC can work up to 4 Msps :

So complete ADC conversion is at its max. speed settings : 0.25 us !

And if using DMA to save data to an array you can sample at 4Msps and fill an array of data at this speed with DMA.

[STuser2]

One final question i have actually 7 ADC channels voltages, currents in which 2 of them are peak values and does not vary much and tried to configure last, i came across the dual mode in the data sheet and this is how i planned.

ADC1 will be master and ADC2 will be slave. I can read the two channels simultaneously at a time for example

ADC1 Ch4, ADC2 Ch1 simultaneously etc. Is my understanding correct?  But i have also seen in the motor control work bench even if the ADC's are configured in independent mode they still able to read the ADC1 and ADC2 simultaneously on an external trigger, so i am bit confused. Can you help me on this? Also i am unable to set the ADC CLk to Asynchronous mode / 1 i can ony /4 -> 170MHz / 4 = 42.5MHz. Thank you in advance for support. 

[Ozone]

> ... i came across the dual mode in the data sheet and this is how i planned.

The details are explained in the MCU reference manual, the DS gives mostly physical characteristics.

Assuming the G4xx ADC implementation is similiar to the F0...F7 devices I worked with, the dual mode can achieve a higher sampling frequency by sampling one input in alternating fashion by two ADCs.
This mode basically reduces internal processing times that way, doubling the maximal sampling frequency.

For a sampling frequency of 20kHz this seems not really relevant.

[waclawek.jan]

Just a word of caution: for simultaneous ADC sampling in 'G4, read carefully also the errata and the 'G4-specific ADC appnote (AN5346).

JW