Diagram for STM32F4 flash stall interrupt latency

[Jnevi.1]

Hi,

some time ago i saw a good picture/diagram which showed the latency of IRQ execution on an stm32 with one flash bank and in comparison with 2 flash banks.

On the controllers with one flash bank the execution is stalled, and with 2 flash banks it is just the 12 cycles latency.

but i can't find this picture anymore. it was somewhere in the ST documentation. Does anybody know where i might have seen this? i looked at the datasheets & ref manual of the stm32f4x7. maybe i looked in th ewrong place or i oversaw it.

thanks for help

[TDK]

Not real sure, but the latency shouldn't depend on how many flash banks it has.

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/beginner-guide-on-interrupt-latency-and-interrupt-latency-of-the-arm-cortex-m-processors

[Jnevi.1]

it depends...if a sector is erased, the execution is stalled. this behaves differently if you have 1 or 2 memory banks (erase and code on different banks)

and there was a nice diagram which showed exactly this bahaviour

[Tesla DeLorean]

I don't recall seeing one, so if I had to guess I'd say it would be in a seminar presentation or application note type document, perhaps an old programming manual document.

@Amel NASRI​ 

[Tesla DeLorean]

It basically stuffs wait states at the processor depending on how long the given write/erase is taking, I don't think the time is absolute as this is self timed, requires a charge-pump to generate high voltages, and aging of the array. The erase time for the larger blocks is very high.

If you have critical / real-time code, you should get your core functionality running out of RAM so you don't get contention on the FLASH causing the second access stalling on completion of the first.