2022-07-12 12:49 PM
Hello,
I am using nucleo F767zi to run LwIP_HTTP_Server_Netconn_RTOS.
According to the MX configurator and according to DocID029041 Rev 6 (SM32F767xx Electrical characteristics) page 143 Fpll_should be [0,95-2,1Mhz].
The mentioned example generates (IMHO) .32 Mhz well outside the forementioned interval.
Details:
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 400;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 9;
RCC_OscInitStruct.PLL.PLLR = 7;
// so => Fpllin = 8 Mhz / M = 8 Mhz / 25 = 0,32MX configurator comes to the same conclusion:
It is a bit strange that an ST example designed (?) for the 767zi board does not comply with the specs?
In the same line the example specifies: (main .c line 72)
/* Configure the system clock to 200 MHz */
SystemClock_Config(); Whereas, according to the code fPllout = fpllin * 400/2 = 64Mhz.
Could it be that I am missing something, because it seems a bit odd (provided my analysis is correct) for ST to provide examples that are outside the specs?
My intention is to use the example as a starting point for my application, but therefore I would assume that the example is compliant with the board, but at first sight it seems not the case?
Solved! Go to Solution.
2022-07-20 5:41 PM
Obviously it's a copy-paste from the boards with a 25 MHz HSE clock, like this one. And there is another bug - both of these boards are using an external clock signal, not a crystal. Therefore for both of these the .PLL.PLLState must be set to RCC_HSE_BYPASS.
For unmodified NUCLEO-F767ZI board the best setting for the maximum speed is:
8 MHz / 4 * 216 / 2 = 216 MHz.
Just in case you don't know:
@Imen DAHMEN, and another way the examples are broken...
2022-07-20 5:41 PM
Obviously it's a copy-paste from the boards with a 25 MHz HSE clock, like this one. And there is another bug - both of these boards are using an external clock signal, not a crystal. Therefore for both of these the .PLL.PLLState must be set to RCC_HSE_BYPASS.
For unmodified NUCLEO-F767ZI board the best setting for the maximum speed is:
8 MHz / 4 * 216 / 2 = 216 MHz.
Just in case you don't know:
@Imen DAHMEN, and another way the examples are broken...
2023-02-24 7:18 AM
Hi,
Thank you for your contribution.
Internal ticket number: 146455
(This is an internal tracking number and is not accessible or usable by customers).
Will be fixed in next F7 maintenance release.
Regards
Mahdy
We’re moving the ST Community to a new platform to give you a better and more reliable community experience.