STPM33/STPM34: Feasibility of Back-to-Back Placement on 6-Layer PCB

[a5]

We are designing a 6-layer PCB with limited board area. The layer stackup is as follows: TOP / GND2 / SIGNAL / POWER / GND5 / BOTTOM.

Due to space constraints, we are planning to place one STPM33 on the TOP side of the board, and another STPM33 rotated 90 degrees directly on the opposite BOTTOM side. Similarly, one STPM34 will be placed on the TOP side, with another STPM34 rotated 90 degrees directly beneath it on the BOTTOM side.

In summary, the board will carry a total of four ICs: one STPM33 and one STPM34 on the TOP side, and one STPM33 and one STPM34 on the BOTTOM side, with each TOP-side IC having its counterpart placed directly behind it on the BOTTOM side.

Please find attached a diagram illustrating the top/bottom placement of the STPM34. Key points of this layout are as follows:

• The power supply pin traces on the TOP and BOTTOM sides are routed nearly overlapping each other.
• The crystals on the TOP and BOTTOM sides are offset from each other so they do not overlap.

We would like to ask the following:

• Is this placement approach feasible from a device characteristics standpoint?
• Are there any concerns or PCB layout precautions we should be aware of regarding this configuration?

[Didier HERROUIN · Accepted solution]

Dear a5,

I don't have any reserve about this placement, as TOP and BOTTOM layers are separated by 4 layers, they will not interfere each other !

During the layout, please take care to keep all the sensors and components as close as possible to the STPM3x analog measuring inputs, as well as the filtering capacitors to each regulated/reference pin.
Maybe, the upper branch of each voltage divider (that consists of three or four resistors) requires more room due to high voltage constraints. In this case, keep the lower resistors (490 ohms in our eval kit schematics) closer to the input pins is sufficient. You can also refer to on-line Design Tip .

A last error to avoid : do not merge the ground signal of ADC inputs (usually connected to VIN1, IIN1, IIN2) with the Ground plane (especially the current sensing lines). Indeed, to avoid current flowing through the ground plane, they must must routed as separate tracks (and as differential pairs with VIP1, IIP1, IIP2) from the sensors to the chipset, and the merge with the ground must be done close to the chipset.

Best regards,

Didier

[a5]

Thank you so much for the thorough response. We’re going to test it out on our prototype using your advice. If we run into any issues, we’ll definitely reach out to the community here again! Thanks,