I have a STM32H755 based board where we use M7 for BareMetal and M4 to run zephyr OS. We enabled IWDG1 in BareMetal and finds that the Flash erase of Bank 1 (M4 bank1, M7 bank 0) from Zephyr cause a reset and reset cause is IWDG1. Couldn't understand what is the dependency. M7 should be able run code from Bank 0 while erase happens on Bank 1.
Now I have enabled IWDG1 in hardware and the reload value is 5 msec. It continuously reboots and I am unable to connect the STMCubeIDE to halt the Cores from rebooting due to IWDG1. I have enabled Debugger0>Device Settings to have 'Suspend watchdog counters while halted "Enable", but IDE connects and disconnects immediately due to watchdog reboot which happens right away after boot. Is there a way to recover from this state.. Since I am not able to connect debugger or STMCube programmer, I am not able to flip the OB bit for hardware watchdog for IWDG1. Need help
