What is the differences between TT and FT mode for usb pins PA12&PA11 in STM32U595?

[Yang Yang]

Hello, ST expert

For GPIO structure, what are the differences between FT and TT mode? Are there any differences for the ESD diode and the other diode in these two modes?

BR

Yang

[Andrew Neil]

https://www.st.com/resource/en/datasheet/stm32u595zi.pdf#page=110

via: https://www.st.com/en/microcontrollers-microprocessors/stm32u595zi.html

[Yang Yang]

Hello, Neil

I know what FT and TT means. The question is what are the differences in the GPIO structure in these two modes? e.g. the state of analog switch in the graph? or any other difference?

BR

Yang

[FBL]

Hi @Yang Yang 

TT pins have clamping diodes to VDD limiting voltage tolerance to VDD + 0.3V. However, FT can tolerate 5V in input/open drain mode without internal pull-up/pull-down.

[Yang Yang]

Hello, FBL

Does that mean there are not any differences about the internal ESD diode and the other diode(circled in the first graph) in these two modes?

BR

Yang

[Andrew Neil]

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@Yang Yang wrote:

I know what FT and TT means.

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But I didn't know that you know!

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@Yang Yang wrote:

the state of analog switch in the graph?

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The graphic you posted says that there is no analogue switch in TT

[Yang Yang]

Hello, Neil

Maybe I do not clearly give a presentation about my concern. PA11&PA12 are vulnerable to ESD spike in our own hardware design. I doubt it maybe caused by TT setting of these pins. So I want to make it clean what's on earth the difference between TT and FT mode taking ESD protection into account. Does FT mode showes better  endurance than TT mode in ESD spike? From my point of view, there are no difference because the ESD diode and the other diode in the graphic I posted are the same in TT and FT mode, am I right?

BR

Yang

[FBL · Accepted solution]

Hi @Yang Yang 

OK it depends on the product, I assume in your case TT pins have clamping diodes to VDD limiting voltage tolerance to VDD + 0.3V used for ESD discharge protection.

The second diode provides a low impedance path to ground when the GPIO voltage goes below VSS. 

Regarding the exact internal implementation of ESD protection in FT differs and I can't provide more details. All needed info are provided in AN4899 section 5.2.

To answer your question, > does FT mode shows better endurance than TT mode in ESD spike?

FT refers mainly to 5V tolerance, while ESD robustness depends on the specific pad design and the product’s ESD ratings, not simply on whether the pin is FT or TT.