2017-06-05 4:03 PM
We are using an STM32F469 in our design. We also utilize the device's DSI interface to a 400X400 LCD (round). We are clocking the micro with a 16MHZ crystal and producing a SYSCLK of 180MHZ. All is good. Now, I am slowing down the SYSCLOCK to 90MHZ to save some power, but in doing so our display gets messed up. The image on the screen is shifted by 50%. Meaning the visible image has walked 200 pixels to the right and wraps back around. How does changing the SYSCLK have this effect?
2017-06-09 6:41 AM
Posted on June 09, 2017 at 15:41
Hi Carrier.Michael,
I think that the AN4861 may bring you some explanation for the issue and help to fix it.
-Amel
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