STM32F30x Definition of Timer signals in DMA mode

[BTrem.1]

I have a basic question on signal definitions used in the Ref Manual. The section on DMA interconnects refers to TIM3_UP, TIM3_UP, etc, and TIM3_Ch3/UP.

First question: What is UP? This is not defined anywhere. Does it mean TIM3 gets updated?

In CubeMX if I setup to use TIM3 Ch3 and Ch4 I can select as dma TIM3_Ch3 but the other choice for Ch4 is TIM3_Ch4/UP. I'm trying to use an external input for TIM3_Ch4 and use COMP4 input for TIM3_Ch3. Is this possible using TIM3?

I was planning on using TIM2_Ch3 and TIM2_Ch4 for this but for other pinout reasons need to change.

It seems like some of the peripheral request signals in Figure 47 RM0316 are not defined very well.

[waclawek.jan]

> What is UP?

The Update event.

The RM explains, what does it mean (basically it's consequence of over/underflow, but there are also other sources to this signal).

> use an external input for TIM3_Ch4 and use COMP4 input for TIM3_Ch3.

Is this possible using TIM3?

I am not quite sure, what's the question here.. If there's a connection from COMP4 to TIM3_CH3, then it can be used for input capture independently from TIM3_CH4. However, you say that DMA shares trigger from Update and TIM3_CH4 (they are essentially OR-ed), so you should probably not use these two at the same time.

> It seems like some of the peripheral request signals in

> Figure 47 RM0316 are not defined very well.

Which signals, namely?

Maybe try to draw some simple diagram explaining what do you intend to achieve.

JW