Posted on August 19, 2014 at 21:41
Having a strange problem; not sure if it's an anomaly of my compiler (IAR) or I'm doing something wrong:
I'm trying to change SYSCLK for the STM32F427, which uses the PLL as the SYSCLK source. The issue is that the RCC_PLLConfig function doesn't seem to have any effect other than to the PLLQ value. I have tried changing the values passed in, and only the last one has any effect according to the register view utility in the IDE.
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 192, 6, 7);
RCC_PLLConfig(RCC_PLLSource_HSE, 24, 300, 2, 7);
These two calls result in the exact same bits set in the PLLCFGR register (according to the IDE).
However, this call:
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 192, 6, 15);
WILL cause a change to the PLLQ0/PLLQ1/PLLQ2/PLLQ3 bits.
I'm using the standard library code for this function:
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
{
/* Check the parameters */
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
assert_param(IS_RCC_PLLM_VALUE(PLLM));
assert_param(IS_RCC_PLLN_VALUE(PLLN));
assert_param(IS_RCC_PLLP_VALUE(PLLP));
assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
RCC->PLLCFGR = PLLM | (PLLN <<
6
) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
(PLLQ << 24);
}
Here's the order of the calls, which work fine to get SYSCLK running at 168MHz, if I comment out the RCC_PLLConfig call and leave the default values:
void ClocksUp(void)
{
/* Enable HSE */
RCC_HSEConfig(RCC_HSE_ON);
/* Wait till HSE is ready */
while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);
//
RCC_PLLConfig(RCC_PLLSource_HSE, 8, 192, 6, 7); //Fix
/* Enable PLL1 */
RCC_PLLCmd(ENABLE);
/* Wait till PLL1 is ready */
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
/* Wait till PLL is used as system clock source */
while (RCC_GetSYSCLKSource() != 0x08);
}
Anyone seen anything like this, or do I need to contact my IDE manufacturer?
Thanks
#sysclk-pll-stm32-iar
