Introduction
The OCTOSPI interface is used in STM32 devices to enhance communication speed with devices like external memories. Achieving the maximum OCTOSPI clock frequency is essential for various applications.
This article explains some factors impacting the OCTOSPI frequency and some recommendations to achieve the maximum.
1. Factors impacting the OCTOSPI frequency
The maximum frequency of OCTOSPI depends on several factors, including: memory characteristics, the specific STM32 devices used, OCTOSPI pins, the operating modes (SDR, DTR, HyperBus), the system clock, the OCTOSPI kernel clock etc. Each of these factors can significantly impact the achievable maximum frequency.
The user should refer to the datasheets of both the STM32 and the memory to find the maximum OCTOSPI frequency and the conditions required to achieve this frequency.
Below some hardware, software, and option byte recommendations to achieve the maximum OCTOSPI frequency are listed.
2. Hardware recommendations
- Make sure to have approximately the same length for all the data lines.
- Reference the plane using GND or VDD. If VDD is used, add a 10nF stitching cap between VDD and GND).
- Use trace impedance: 50 Ω for single-ended and 100 Ω for differential pairs (CLK/NCLK).
- Design a maximum trace length less than 120 mm. If the signal trace exceeds this trace-length/speed criterion, then a termination should be used.
- Avoid using multiple signal layers for the data signal routing.
- Route the clock signal at least three times the width of the trace away from other signals.
- Match the trace lengths for the data group within ± 10 mm of each other. This practice is applied to reduce any excessive skew. Serpentine traces can be used to match the lengths.
- Avoid using a serpentine routing for the clock signal. It is recommended to use via as little as possible for the whole path. A via alters the impedance and adds a reflection to the signal.
- Avoid discontinuities on high-speed traces (vias, SMD components).
- Ensure that the voltage and capacity load are within the specified ranges.
3. Software recommendations
- Configure all GPIOs for very high-speed operation.
- Check the write zero latency in the OCTOSPI configuration for HyperBus mode.
- Activate the I/O compensation cell.
- Set VOS level to VOS0.
- Enable sample shifting (SSHIFT) bit with STR mode and disable with DTR mode.
- Enable the delay hold quarter cycle (DHQC) with DTR mode and disable with STR mode.
- Use the delay block (DLYB), if it is available in STM32 device when in DTR mode.
- Use DQS if the memory supports it.
- Check the FIFO threshold. This FAQ explains how to configure FIFO with the OCTOSPI interface.
- Configure the drive strength (memory side) to tune output signal strength.
4. Option bytes
- HSLV is activated when VDD ≤ 2.5 V.
- HSLV is deactivated when VDD ≥ 2.5 V.
If the memory operation voltage is below the 2.5 V, we recommend enabling the HSLV feature for the used GPIOs to increase their maximum speed at low voltage. This feature must be enabled in the option bytes. This FAQ describes how to enable the HSLV in STM32H7R/S.
If you follow these recommendations and you are unable to reach the maximum OCTOSPI frequency, we suggest that you create a post in the ST community product forums for further assistance.
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