USART_Init() gets wrong freq info from RCC_GetClocksFreq()

kermespersialainen · ‎2010-09-28

Posted on September 28, 2010 at 12:53

kermespersialainen · ‎2011-05-17

Posted on May 17, 2011 at 14:09

Edit: Clearly PLL is the SYSCLK source because the chip runs at 20MHz (I can get 5MHz out of GPIO pins by toggling them).

Can it be that I have only a 20MHz F100CBT6 ''evaluation version'' instead of real 24MHz F100CBT6B ?

kermespersialainen · ‎2011-05-17

Posted on May 17, 2011 at 14:09

It seems there is a problem regarding values in RCC_CFGR and RCC_CFGR2.

It seems that the clock configuration code SetSysClockTo24() for example writes to RCC_CFGR correctly to divide HSE clock by two (PREDIV1 and PREDIV1_Div2 bits set).

But RCC_GetClocksFreq() uses RCC_CFGR to determine if PREDIV1 is used, and then reads RCC_CFGR2 to get the divisor, but bit 0 of CFGR2 does not reflect the value of RCC_CFGR bit 17 (PLLXTPRE or PREDIV1_Div2).

So CFGR2 and CFGR should both get updated if other one is written, right?

Is this a silicon bug, startup code bug or RCC module code bug, and what would be the best way to fix this while waiting next peripherals library with updated RCC module code?