Can ST please review the requirement of I2SDIV > 2 in SPI/I2S of 'F2/'F4?

[waclawek.jan]

In SPIx_I2SPR, I2SDIV=1 is probably fine as long as ODD is kept 0.

https://community.st.com/s/question/0D50X00009XkYmHSAV/f2f4-i2s-extclock

This constraint probably unnecessary puts pressure onto using higher than necessary I2S clock,

and restricts certain clock combinations.

Can ST please review this requirement.

Thanks,

JW