Posted on January 30, 2016 at 23:13See line 678 :
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
The intend is to check System clock switch status (SWS field of RCC_CFGR) after writing to System clock switch (SW field of RCC_CFGR). But the definition of RCC_SYSCLKSOURCE_STATUS_PLLRCLK
is wrong. As a result that statement never gets false which leads to timeout. In turn, that leads to skipping initialization of PPRE1 and PPRE2 of RCC_CFGR. The consequence is: APB1 and APB2 clocks are the same as AHB clock when AHB prescaler = 1. So, if SYSCLK is 180 MHz the APB1 will run at the same clock (should be 45 MHz max) ! Wow!
Conclusion: The definition of
RCC_SYSCLKSOURCE_STATUS_PLLRCLK s
hould point to bits 3:2 instead of 1:0 of RCC_CFGR register
#stm32f4x-hal-library
