ADC with DMA and timer

[KD�?b]

Hello

my MCU stm32f411ceu

I am using ADC with DMA and timer. I am sampling signal at 48 khz using TIM2. It means that every 21 us there is a new measurement. My ADCCKL taking into account prescaler is 6 Mhz. The bit resolution is 12 bits. If i my sampling time is 28 cycles that means my conversion time of one sample is 6,66 us. I am using half and fullcallbacks EOC. When I change sampling time to 84 cycles, the conversion time of one sample is 16 us. I try to sample 1khz sinusoid .But when i take 1000 samples using sampling time 84 cycles there are more sinusoids than when sampling time is 28 cycles, meaning the frequency of sin is higher. I thought that if the conversion time is less than 21 us (so the conversion of a sample is completed before next measurement), then the sampling time should not impact of the frequency of measurement, but in my case it does. Am I thinking wrong? Thanks for help in advance.

[TDK]

Your logic is correct. Note that there is an additional ~12 cycles needed for each conversion on top of the sampling time. This doesn't affect your logic, however.

The issue is likely in your code or in your assumptions.