VN9D30Q100 PWM control

[zhi_sai]

Dear sir:
I was used VN9D30Q100FTR 6-channel high-side driver for automotive electronic products，the schematic diagram below：

According to the datasheet, the PWM clock should be provided via the PWM_CLK input, but there was also this note about the PWM fallback clock:

"When PWMCLOCKLOW warning flag is set, an internal fallback clock (at a typical frequency of 400 kHz) is used
to substitute the external one."

My question was ：Can there be PWM signal output for controlling the high side？

[Peter BENSCH]

Welcome @zhi_sai, to the community!

I do not fully understand your question; perhaps you could describe in a little more detail what you would like to achieve?

The VN9D30Q100F does support PWM control of the high-side outputs. PWM_CLK is an input clock for the internal PWM engine, not a PWM output pin. The device generates the PWM internally and drives OUT0…OUT5 accordingly. The fallback clock at about 400kHz is only an internal replacement clock used when the external PWM_CLK is missing or too slow.

Regards
/Peter