SSC Driver support LSM6DSV for QCS8550 board

[sagarpatel1]

Hello Team,

We are using Qulacomm board QCS8550 Aikri kit with LE r90 release for production, In that there is SSC driver support of LSM6DSV

Our setup includes two LSM6DSVTR IMU sensors, and we are attempting to read and write sensor data over SSC using an I2C interface. The I2C bus has been configured in the JSON configuration file for the LSM6DSVTR.

Use Case Requirements:

Configuring both IMU sensors using the SSC driver with an I2C-based interface Using interrupt pins for data-ready signaling

Specifically:

INT2 must support an external pulse:

Current Status:

In the current driver implementation located at:

source/adsp_proc/ssc_drivers/lsm6dsv

From the driver code analysis, we observed that data is currently being received using a FIFO-based mechanism.

Additionally, it appears that the default driver implementation supports only the INT1 interrupt, while there is no implementation observed for INT2.

Problem Statement:

Our requirement is to generate an INT2 pulse for every sensor data sample.

For example, if the configured sample rate is 10 Hz, we expect one INT2 pulse per sample.

Currently we are not receiving any interrupt on INT2 pin of LSM6DSV,

Can you please help us to how to produce the DRDY interrupt on INT2 pin for SSC driver implementation ?

Lets us know if you required any additional information.

[Federica Bossi · Accepted solution]

Hi @sagarpatel1 ,

To generate a DRDY pulse on INT2 for the LSM6DSVTR with the SSC driver, FIFO configuration alone is not enough. The driver must explicitly enable and route the data-ready signal to INT2 in the sensor registers.

[sagarpatel1]

Hello,

Thanks for the reply.

As per your suggestion, can you please help us to achevie that, or can you please provide the SSC driver for DRDY pulse on INT2 for QCS8550 SSC framework.

[sagarpatel1]

@Federica Bossi is there any update ? Can you please help me to implement it.