Posted on December 28, 2017 at 10:11I have this
http://www.kynix.com/Parts/3294011/SIT8009AC-11-18E-125.000000E.html
MEMS oscillator at 125MHz frequency (also the same with an OSC52 from SiWard at 25MHz) followed by a 1-to-4 clock driver to distrubute the clock to multiple ICs.
When layouting, I always find myself asking what is the 'best' layout practices for them, since they are high speed signal sources and since I almost always have EMC problems related with these frequencies. This doesn't mean of course that the source of the problems are these oscillators. But I nevertheless look for ways to improve the layout at this corner.
Do you have any specific guidelines you follow when you layout such components?
Some of which I use are the following:
- The driver is physically placed close to the oscillator
- The decoupling capacitors are carefully placed close to the supply pins
- I typically use a ferrite bead to create a filter at the power supply
- On all layers underneath the oscillator and the driver I don't route any signals at all
- All clock outputs are provided with a series resistor used for termination purposes
Do you have anything else to propose?
- For example would using ferrite beads at the clock outputs help anyhow? I mean by dumping higher clock harmonics
- One 'expert' once told me to do the following: practically to use a separate 3-sided GND 'Island' (more like a peninsula) underneath the components which is only connected on one side to the rest of the GND plane. The side where also the outputs go out. Do you think such an approach would help? I suppose this ensures that you don't induct noise on other signals nearby. Does it do anything else?
I want to share you with some useful articles:
http://www.apogeeweb.net/article/19.html
